1/7 n over voltage protection for 3.3v 5v and 12v without external com- ponents n under voltage protection for 3.3v 5v and 12v without external com- ponents n over voltage protection for -12v or -5v with external components n externally adjustable under volt- age blanking during power up n power good input/output n externally adjustable pg delay n fault output n remote output n externally adjustable remote delay n precision voltage reference n 2kv esd protection description the tsm112 integrated circuit incorporates all sensing circuitry to regulate and protect from over voltage and under voltage a multiple output power supply (3.3v, 5v and 12v). tsm112 incorporates all the necessary functions for housekeeping features which allow safe oper- ation in all conditions, and very high system inte- gration. tsm112 integrates a precise voltage reference. application n pc smps triple power line housekeeping ic (3.3v 5v 12v) order code n = dual in line package (dip) d = small outline package (so) - also available in tape & reel (dt) pin connections (top view) part number temperature range package marking nd TSM112CN 0 to 85c tsm112c tsm112cd 0 to 85c m112 n dip14 (plastic package) d so14 (plastic micropackage) vcc rem trem tpg pg vs33 vs5 vs12 pi tuv ep gnd vref 10 9 8 7 6 5 4 3 2 1 11 12 13 14 faul t january 2001 tsm112 3.3v 5v 12v housekeeping ic obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
tsm112 2/7 pin description absolute maximum ratings operating conditions name pin # type function vcc 14 power supply positive power supply line gnd 7 power supply ground line. 0v reference for all voltages vs12 3 analog input over and under voltage sense input dedicated to the 12v line 1) vs5 2 analog input over and under voltage sense input dedicated to the 5v line 1) vs33 1 analog input over and under voltage sense input dedicated to the 3.3v line 1) tuv 6 timing capacitor adjustable under voltage blanking delay at power up (setting capacitor) fault 13 open collector fault output. fault is high when over or under voltage has been detected pi 5 analog input power good input. detection of the power conditions pg 12 open collector power good output. pg output is high when the power conditions are ok tpg 11 timing capacitor adjustable power good delay (setting capacitor) rem 9 logic input input remote control of the complete system by the motherboard ( m controller). remote is active high. switch off/on of the power supply. reset of the complete system after a fault activation. trem 10 timing capacitor adjustable remote delay (setting capacitor). vref 8 voltage reference 2.5v reference for all voltages ep 4 analog input extra protection circuit. can be used for -12v or -5v over voltage protection. 1. over and under voltage inputs can go higher than vcc within the allowed max rating range symbol dc supply voltage value unit vcc dc supply voltage 1) 25 v iout output current power good 30 ma io output current for the voltage reference 20 ma vfault fault ouput 5 v top operating free air temperature range -55 to 125 c pd power dissipation 0.7 w tstg storage temperature -55 to 150 c esd electrostatic discharge 2 kv tuv adjustable under voltage blanking at power up 5 v ep extra protection 5 v pi power good input 5 v pg power good output 5 v tpg adjustable power good delay 5 v rem remote control 5 v trem adjustable remote delay 5 v 1. all voltage values, except differential voltage are with respect to network ground terminal. symbol parameter value unit vcc dc supply conditions 4.5 to 24 v toper operating free air temperature range 0 to 85 c obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
tsm112 3/7 electrical characteristics tamb = 25c and vcc = 17v (unless otherwise specified) symbol parameter test condition min typ max unit total current consumption icc total supply current 3 5 ma over voltage and under voltage protection vov33 over voltage sense 3.3v input can go higher than vcc 3.8 4 4.2 v vov5 over voltage sense 5v input can go higher than vcc 5.8 6.1 6.4 v vov12 over voltage sense12v input can go higher than vcc 13.4 14.2 15 v vuv33 under voltage sense 3.3v 2.1 2.3 2.5 v vuv5 under voltage sense 5v 3.7 4 4.3 v vuv12 under voltage sense 12v 9.2 10 10.8 v vep extra over voltage protection threshold 1.28 v tfault fault delay before latching internally fixed delay 100 m s under voltage blanking during power up tuv under voltage blanking during power up (vcc rising) cuv = 2.2 m f adjustable blanking 100 300 500 ms thuv blanking threshold 1.28 v power good (pg) vpgth power good voltage threshold 1.28 v vpghyst power good voltage threshold hysteresis 70 mv vpgol low output open collector saturation voltage collector current = 15ma 0.4 v ipgoh high output open collector leakage current pg output = 5v 1 m a tpgr power good output rise time load capacitor = 100pf 1 m s tpgf power good output fall time load capacitor = 100pf 1 m s tpg power good adjustable delay load capacitor cpg=2.2 m f 100 300 500 ms pith power input detection threshold 1.28 v fault vfaultol fault output saturation voltage level ifault = 1ma 1 v ifaultoh fault output leakage current level vfault = 5v 1 a remote control (rem) vremth remote on/off input voltage threshold 0.7 0.8 1 v vremih high input remote voltage 3.3 3.4 v iremil low input remote saturation current 0.5 ma trem1 remote adjustable delay on to off load capacitor crem=0.1 m f 40 50 60 ms trem2 remote adjustable delay off to on load capacitor crem=0.1 m f 40 50 60 ms voltage reference vref internal voltage reference io = 0ma 2.46 2.5 2.54 v regline line regulation io = 0ma 4.5v tsm112 4/7 figure 1 : figure 1: application schematic figure 2 : internal schematic primary rect. main conv. 12v 5v 3.3v aux. conv. 5vstby vcc ~ tsm112 over & undervoltage protection reference logic sequencer 12v 5v 3.3v 5vstby pg rem fault pwm + opto pwm + opto + vref + vref ovp vref housekeeping logic secondary vcc vs12 vs5 vs33 pg rem to motherboard from main conv. power supply output 12v 5v 3.3v 12v 5v 3.3v pi to uvp trem tpg uv blank tuv fault gnd tsm112 vref ep obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
tsm112 5/7 figure 3 : figure 3 : detailed internal schematic vref ovp vov12 vs12 vs5 vs33 0.8v fault rem pg 3.47v s r q vcc 1.25v pi vref in 12v out 12v in 5v out 5v in 3.3v out 3.3v to motherboard uvp vuv12 tfault tpg tpg cpg trem cuv tuv vref ovp vov5 uvp vuv5 vref ovp vov33 uvp vuv33 ovp uvp tsm112 crem trem tuv vcc power up uv blanking gnd vref 1.25v ovp ep 1k obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
6/7 tsm112: housekeeping ic. tsm112 is a one chip solution for all pc smps: it integrates on one chip the housekeeping circuitry (over voltage and under voltage protections, with adequate sequencing). triple power line protection. the tsm112 housekeeping circuit is dedicated to 3.3v, 5v and 12v power lines protection. it inte- grates a precision voltage reference, a triple over voltage protection circuit and a triple under voltage protection circuit as well as all the neces- sary logic and transient timing management cir- cuits for optimal and secure communication with the motherboard, during start up, switch off and stabilized conditions. over voltage protection the over voltage protection circuit is made of three comparators with internal voltage thresholds (vov33, vov5, vov12) which do not require any external components for proper operation. the outputs of these three comparators are ored. under voltage protection the under voltage protection circuit is made of three comparators with internal voltage thresholds (vuv33, vuv5, vuv12) which do not require any external components for proper operation. the outputs of these three comparators are ored, and blanked by an internal delay circuitry (power up blanking - tuv) which can be adjusted with an ex- ternal capacitor (cuv). this allows that during power up, the under voltage protection circuit is in- hibited. latch off the over voltage and under voltage circuits out- puts are again ored before activating a latch. when activated, this latch commands the full switch off of the three main power lines (3.3v, 5v, 12v) by an external link between the house- keeping and the primary pwm circuits via the main optocoupler or any other device . note that the under voltage circuit, after power up uv blanking, bears no other delay to the latch setting input whereas the over voltage circuit bears an additional tfault delay time. this allows an effi- cient protection against output short circuit con- ditions. power good the over voltage and under voltage circuits are ored to switch the power good output active (pg) to warn the motherboard that the voltage of at least one of the three power lines is out of range. the pg activation bears an internal tpg delay cir- cuitry which can be adjusted with an external ca- pacitor (cpg). remote control thanks to this information link to the motherboard, a resetting signal to the latch is achievable with the remote pin (rem). when the remote pin is active, the external fault link between house- keeping circuit and the pwm generator is active (high = pwm off) and the pg pin is active (high). note that to reset effectively the latch, a minimum width remote pulse should be applied thanks to an internal delay circuitry (trem) which can be ad- justed with an external capacitor (crem). tsm112 principle of operation and application hints obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
tsm112 7/7 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. ? the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco singapore - spain - sweden - switzerland - united kingdom ? http://www.st.com package mechanical data 14 pins - plastic package dim. millimeters inches min. typ. max. min. typ. max. a1 0.51 0.020 b 1.39 1.65 0.055 0.065 b 0.5 0.020 b1 0.25 0.010 d 20 0.787 e 8.5 0.335 e 2.54 0.100 e3 15.24 0.600 f 7.1 0.280 i 5.1 0.201 l 3.3 0.130 z 1.27 2.54 0.050 0.100 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
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